TY - JOUR
T1 - A fully integrated multi-CPU, processor graphics, and memory controller 32-nm processor
AU - Yuffe, Marcelo
AU - Mehalel, Moty
AU - Knoll, Ernest
AU - Shor, Joseph
AU - Kurts, Tsvika
AU - Altshuler, Eran
AU - Fayneh, Eyal
AU - Luria, Kosta
AU - Zelikson, Michael
PY - 2012/1
Y1 - 2012/1
N2 - This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of integration. The paper describes the chip floor plan, the power delivery network, energy conservation techniques, the clock generation and distribution, the on-die thermal sensors, and a novel debug port.
AB - This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of integration. The paper describes the chip floor plan, the power delivery network, energy conservation techniques, the clock generation and distribution, the on-die thermal sensors, and a novel debug port.
KW - Clocking
KW - Intel second-generation core
KW - low Vccmin
KW - modularity
KW - power gates
KW - thermal sensors
UR - http://www.scopus.com/inward/record.url?scp=84870642148&partnerID=8YFLogxK
U2 - 10.1109/jssc.2011.2167814
DO - 10.1109/jssc.2011.2167814
M3 - ???researchoutput.researchoutputtypes.contributiontojournal.article???
AN - SCOPUS:84870642148
SN - 0018-9200
VL - 47
SP - 194
EP - 205
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 1
M1 - 6044730
ER -
