A fully integrated multi-CPU, GPU and memory controller 32nm processor

Marcelo Yuffe, Ernest Knoll, Moty Mehalel, Joseph Shor, Tsvika Kurts

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

98 Scopus citations

Abstract

This paper describes the 32nm Sandy Bridge processor that integrates up to 4 high performance Intel Architecture (IA) cores, a power/performance optimized graphic processing unit (GPU) and memory and PCIe controllers in the same die. The Sandy Bridge architecture block diagram is shown in Fig. 15.1.1 and the floorplan of a four IA-core version is shown in Fig. 15.1.2. The Sandy Bridge IA core implements an improved branch prediction algorithm, a micro-operation (Uop) cache, a floating point Advanced Vector Extension (AVX), a second load port in the L1 cache and bigger register files in the out-of-order part of the machine; all these architecture improvements boost the IA core performance without increasing the thermal power dissipation envelope or the average power consumption (to preserve battery life in mobile systems). The CPUs and GPU share the same 8MB level-3 cache memory. The data flow is optimized by a high performance on die interconnect fabric (called "ring") that connects between the CPUs, the GPU, the L3 cache and the system agent (SA) unit that houses a 1600MT/s, dual channel DDR3 memory controller, a 20-lane PCIe gen2 controller, a two parallel pipe display engine, the power management control unit and the testability logic. An on die EPROM is used for configurability and yield optimization.

Original languageEnglish
Title of host publication2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages264-265
Number of pages2
ISBN (Print)9781612843001
DOIs
StatePublished - 2011
Externally publishedYes
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: 20 Feb 201124 Feb 2011

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Country/TerritoryUnited States
CitySan Francisco, CA
Period20/02/1124/02/11

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