A Data Flow Technique for the Efficient Design of a Class of Parallel Non-Data Flow Signal Processors

This paper presents a system, called net optimization and resource allocation (NORA), for the evaluation and programming of parallel signal processors, based on a data flow representation of the signal processing application. The main feature of this approach is that the scheduling and resource allocation can be done at compile time. It is made possible by the fact that most signal processing algorithms have a constant data flow. The resulting hardware is much simpler, because no overhead is needed for the real-time scheduling as in usual data flow systems. Therefore a realization can easily be obtained using either commercially available components or VLSI technology. The proposed system comprises four main components: 1) a vector oriented data flow compiler for the translation of a high level language description of algorithms into a data flow graph; 2) a critical path analysis for the evaluation of the minimal computation time of the algorithm, where we assume block scheduling; 3) a schedule optimization for the determination of the minimal computation time under limited resources, not taking into account limitations imposed by the interconnection structure and temporary storage; and 4) a combined schedule optimization and resource allocation that maps a signal processing application onto a given hardware configuration and generates a formal microprogram.