A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process

On complex system-on-chips (SOCs), a compact on-die analog-to-digital converter (ADC) is required in high-volume testing, in order to reduce the test time and improve the test coverage of on-die analog intellectual properties (IPs). This paper presents a compact first-order ΣΔ modulator for on-die voltage measurements in such applications. The primary design focus is to achieve a highly compact area so that many instances can be integrated to cover the testing of multiple analog IPs on a single chip die. The proposed modulator deploys an inverter-based architecture which enables the aggressive area reduction. There are two new additional enhancements: 1) hardware dithering to minimize the limit-cycling effect and 2) time-multiplexed pseudodifferential operation for common mode rejection. The modulator exhibits a figure of merit (FOM) of 554.7 fJ/conv-step, in spite of the compact area of only 0.00023 mm².