A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The silicon area and power consumption of ultra-low power (ULP) applications is often dominated by embedded memories [1] , [2]. A popular approach for power reduction is scaling the supply voltage ( V DD ) down to the sub-threshold (sub- V T ) region, however, the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at scaled voltages [3] , [4].

Original languageEnglish
Title of host publication2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728135236
DOIs
StatePublished - 14 Oct 2019
Event2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 - San Jose, United States
Duration: 14 Oct 201917 Oct 2019

Publication series

Name2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

Conference

Conference2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Country/TerritoryUnited States
CitySan Jose
Period14/10/1917/10/19

Bibliographical note

Funding Information:
IV. ACKNOWLEDGMENTS This work was supported by the Israel Science Foundation (ISF) under grant number 996/2018.

Publisher Copyright:
© 2019 IEEE.

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