Abstract
Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of the system. Embedded memories, often implemented with six-transistor static random access memory (SRAM) cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel PA attacks due to the correlation between their current characteristics and written data. To provide resiliency to these types of attacks, we propose a security-oriented 7T SRAM cell, which incorporates an additional transistor to the original 6T SRAM implementation and a two-phase write operation, which significantly reduces the correlation between the stored data and the power consumption during write operations. The proposed 7T SRAM cell was implemented in a 28 nm technology and demonstrates over 1000 × lower write energy standard deviation between write '1' and '0' operations compared to a conventional 6T SRAM. In addition, the proposed cell has a 39%-53% write energy reduction and a 19%-38% reduced write delay compared to other PA resistant SRAM cells.
Original language | English |
---|---|
Article number | 8572791 |
Pages (from-to) | 1396-1400 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 66 |
Issue number | 8 |
DOIs | |
State | Published - Aug 2019 |
Bibliographical note
Publisher Copyright:© 2018 IEEE.
Keywords
- Static random access memory (SRAM)
- differential power analysis (DPA)
- side-channel attacks (SCA)