Abstract
An ultrahigh throughput low-density parity-check (LDPC) decoder with an unrolled full-parallel architecture is proposed, which achieves the highest decoding throughput compared to previously reported LDPC decoders in the literature. The decoder benefits from a serial message-transfer approach between the decoding stages to alleviate the well-known routing congestion problem in parallel LDPC decoders. Furthermore, a finite-alphabet message passing algorithm is employed to replace the VN update rule of the standard min-sum (MS) decoder with lookup tables, which are designed in a way that maximizes the mutual information between decoding messages. The proposed algorithm results in an architecture with reduced bit-width messages, leading to a significantly higher decoding throughput and to a lower area compared to an MS decoder when serial message transfer is used. The architecture is placed and routed for the standard MS reference decoder and for the proposed finite-alphabet decoder using a custom pseudohierarchical backend design strategy to further alleviate routing congestions and to handle the large design. Postlayout results show that the finite-alphabet decoder with the serial message-transfer architecture achieves a throughput as large as 588 Gb/s with an area of 16.2 mm2 and dissipates an average power of 22.7 pJ per decoded bit in a 28-nm fully depleted silicon on isulator library. Compared to the reference MS decoder, this corresponds to 3.1 times smaller area and 2 times better energy efficiency.
| Original language | English |
|---|---|
| Article number | 2766925 |
| Pages (from-to) | 329-340 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 26 |
| Issue number | 2 |
| DOIs | |
| State | Published - Feb 2018 |
| Externally published | Yes |
Bibliographical note
Publisher Copyright:© 2017 IEEE.
Funding
He has held visiting positions at the Laboratoire des Signaux et Systèmes, Ecole Supérieure dElectricité, Toulouse, France, in 2004, the Communication Theory Laboratory, ETH Zürich, Zürich, Switzerland, in 2007, and the École Nationale Supérieure d’Electrotechnique, d’Electronique, d’Informatique et d’Hydraulique de Toulouse, Toulouse, France, in 2011. He currently holds a tenured Associate Professor position with the Institute of Telecommunications, Vienna University of Technology. He has directed or actively participated in several research projects funded by the Austrian Science Fund, by the Viennese Science and Technology Fund, and by the European Union. He has published over 200 scientific articles in international journals, conference proceedings, and edited books. He is the coeditor of the book Wireless Communications Over Rapidly Time-Varying Channels (New York, NY, USA: Academic, 2011). His current research interests include wireless networks, statistical signal processing, information theory, and big data. Manuscript received March 10, 2017; revised June 10, 2017 and August 27, 2017; accepted October 4, 2017. Date of publication November 16, 2017; date of current version January 19, 2018. This work was supported by the Swiss National Science Foundation under Project 200021-153640. (Corresponding author: Reza Ghanaatian.) R. Ghanaatian, A. Balatsoukas-Stimming, C. Müller, A. Teman, and A. Burg are with the Telecommunications Circuits Laboratory, EPFL Lausanne, 1015 Lausanne, Switzerland (e-mail: [email protected]; [email protected]; [email protected]; adam.teman@ epfl.ch; [email protected]). Mr. Burg is also a member of the EURASIP SAT SPCN and the IEEE TC-DISPS. In 2000, he was a recipient of the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. He was also a recipient of ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a 4-year grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship. With his students he received the Best Paper Award from the EURASIP Journal on Image and Video Processing in 2013 and the Best Demo/Paper Awards at the ISCAS 2013, ICECS 2013, and ACSSC 2007. He has served on the TPC of various conferences on signal processing, communications, and VLSI. He was the TPC Co-Chair for VLSI–SoC 2012 and the TCP Co-Chair for the ESSCIRC 2016 and SiPS 2017. He served as an Editor for the IEEE TRANSACTION OF CIRCUITS AND SYSTEMS in 2013 and is on the Editorial board of the Springer Microelectronics Journal and the MDPI Journal on Low-Power Electronics and its Applications.
| Funders | Funder number |
|---|---|
| Viennese Science and Technology Fund | |
| European Commission | |
| Schweizerischer Nationalfonds zur Förderung der Wissenschaftlichen Forschung | 200021-153640 |
| Austrian Science Fund |
Keywords
- 28-nm FD-SOI
- Finite-alphabet decoder
- Low-density parity-check (LDPC) code
- Min-sum (MS) decoding
- Unrolled architecture
