A 512 kb 0.069 μm2 Logic 3T GCRAM with 27 μs Retention Time at 85°C in 16 nm FinFET

A. Yigit; A. Avcioglu; R. Giterman; L. Johansson; I. Lavi; E. Leizerovitz; X. Li; C. Mueller; E. Rotem; Y. Shoshan; A. Teman; S. Yuzhaninov; A. Burg

doi:10.1109/esserc66193.2025.11214105

A 512 kb 0.069 μm² Logic 3T GCRAM with 27 μs Retention Time at 85°C in 16 nm FinFET

A. Yigit
, A. Avcioglu
, R. Giterman
, L. Johansson
, I. Lavi
, E. Leizerovitz
, X. Li
, C. Mueller
, E. Rotem
, Y. Shoshan
, A. Teman
, S. Yuzhaninov
, A. Burg

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

We present the highest-density reported single-supply Gain-Cell (GCRAM) memory macro (0.069 μ m² bitcell) incorporating low-overhead write and retention WL-assist and a PVT-compensating dynamic reference generation. The proposed bitcell introduces a novel flipped topology that improves steady-state storage node voltage and retention performance, enabling read currents that are largely independent of data retention time. The 512 kb (1024 bit wide) logic-rule macro area in 16 nm FinFET is 0.044 mm². Measurements demonstrate a retention time of 147 μ s at 25° C, which is the longest GCRAM retention time reported in 16 nm. The write and read currents of 16 nA/MHz/bit and 26nA/MHz/bit achieve significant power reduction over SRAM.

Original language	English
Title of host publication	Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
Publisher	IEEE Computer Society
Pages	293-296
Number of pages	4
ISBN (Electronic)	9798331525392
DOIs	https://doi.org/10.1109/esserc66193.2025.11214105
State	Published - 2025
Externally published	Yes
Event	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 - Munich, Germany Duration: 8 Sep 2025 → 11 Sep 2025

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
Country/Territory	Germany
City	Munich
Period	8/09/25 → 11/09/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

GCRAM
SRAM
embedded memories
gain-cell

Access to Document

10.1109/esserc66193.2025.11214105

Cite this

Yigit, A., Avcioglu, A., Giterman, R., Johansson, L., Lavi, I., Leizerovitz, E., Li, X., Mueller, C., Rotem, E., Shoshan, Y., Teman, A., Yuzhaninov, S., & Burg, A. (2025). A 512 kb 0.069 μm² Logic 3T GCRAM with 27 μs Retention Time at 85°C in 16 nm FinFET. In Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 (pp. 293-296). (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/esserc66193.2025.11214105

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abstract = "We present the highest-density reported single-supply Gain-Cell (GCRAM) memory macro (0.069 μ m2 bitcell) incorporating low-overhead write and retention WL-assist and a PVT-compensating dynamic reference generation. The proposed bitcell introduces a novel flipped topology that improves steady-state storage node voltage and retention performance, enabling read currents that are largely independent of data retention time. The 512 kb (1024 bit wide) logic-rule macro area in 16 nm FinFET is 0.044 mm2. Measurements demonstrate a retention time of 147 μ s at 25° C, which is the longest GCRAM retention time reported in 16 nm. The write and read currents of 16 nA/MHz/bit and 26nA/MHz/bit achieve significant power reduction over SRAM.",

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author = "A. Yigit and A. Avcioglu and R. Giterman and L. Johansson and I. Lavi and E. Leizerovitz and X. Li and C. Mueller and E. Rotem and Y. Shoshan and A. Teman and S. Yuzhaninov and A. Burg",

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doi = "10.1109/esserc66193.2025.11214105",

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Yigit, A, Avcioglu, A, Giterman, R, Johansson, L, Lavi, I, Leizerovitz, E, Li, X, Mueller, C, Rotem, E, Shoshan, Y, Teman, A, Yuzhaninov, S & Burg, A 2025, A 512 kb 0.069 μm² Logic 3T GCRAM with 27 μs Retention Time at 85°C in 16 nm FinFET. in Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. European Solid-State Circuits Conference, IEEE Computer Society, pp. 293-296, 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025, Munich, Germany, 8/09/25. https://doi.org/10.1109/esserc66193.2025.11214105

A 512 kb 0.069 μm² Logic 3T GCRAM with 27 μs Retention Time at 85°C in 16 nm FinFET. / Yigit, A.; Avcioglu, A.; Giterman, R. et al.
Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society, 2025. p. 293-296 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - We present the highest-density reported single-supply Gain-Cell (GCRAM) memory macro (0.069 μ m2 bitcell) incorporating low-overhead write and retention WL-assist and a PVT-compensating dynamic reference generation. The proposed bitcell introduces a novel flipped topology that improves steady-state storage node voltage and retention performance, enabling read currents that are largely independent of data retention time. The 512 kb (1024 bit wide) logic-rule macro area in 16 nm FinFET is 0.044 mm2. Measurements demonstrate a retention time of 147 μ s at 25° C, which is the longest GCRAM retention time reported in 16 nm. The write and read currents of 16 nA/MHz/bit and 26nA/MHz/bit achieve significant power reduction over SRAM.

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Yigit A, Avcioglu A, Giterman R, Johansson L, Lavi I, Leizerovitz E et al. A 512 kb 0.069 μm² Logic 3T GCRAM with 27 μs Retention Time at 85°C in 16 nm FinFET. In Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society. 2025. p. 293-296. (European Solid-State Circuits Conference). doi: 10.1109/esserc66193.2025.11214105