A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS

Pascal Meinerzhagen; Oskar Andersson; Babak Mohammadi; Yasser Sherazi; Andreas Burg; Joachim Neves Rodrigues

doi:10.1109/ESSCIRC.2012.6341319

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-V_T memory in 65nm CMOS

Pascal Meinerzhagen, Oskar Andersson, Babak Mohammadi, Yasser Sherazi, Andreas Burg, Joachim Neves Rodrigues

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

29 Scopus citations

Abstract

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-V_T) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub-V_T storage arrays and fill the gap of missing sub-V_T memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D-latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220 mV) and a total energy of 14 fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65nm CMOS reported to date.

Original language	English
Title of host publication	2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
Pages	321-324
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2012.6341319
State	Published - 2012
Externally published	Yes
Event	38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France Duration: 17 Sep 2012 → 21 Sep 2012

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	38th European Solid State Circuits Conference, ESSCIRC 2012
Country/Territory	France
City	Bordeaux
Period	17/09/12 → 21/09/12

Funding

Funders	Funder number
Schweizerischer Nationalfonds zur Förderung der Wissenschaftlichen Forschung	119057

Access to Document

10.1109/ESSCIRC.2012.6341319

Cite this

Meinerzhagen, P., Andersson, O., Mohammadi, B., Sherazi, Y., Burg, A., & Rodrigues, J. N. (2012). A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-V_T memory in 65nm CMOS. In 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012 (pp. 321-324). Article 6341319 (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2012.6341319

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abstract = "Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub-VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D-latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220 mV) and a total energy of 14 fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65nm CMOS reported to date.",

author = "Pascal Meinerzhagen and Oskar Andersson and Babak Mohammadi and Yasser Sherazi and Andreas Burg and Rodrigues, {Joachim Neves}",

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Meinerzhagen, P, Andersson, O, Mohammadi, B, Sherazi, Y, Burg, A & Rodrigues, JN 2012, A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-V_T memory in 65nm CMOS. in 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012., 6341319, European Solid-State Circuits Conference, pp. 321-324, 38th European Solid State Circuits Conference, ESSCIRC 2012, Bordeaux, France, 17/09/12. https://doi.org/10.1109/ESSCIRC.2012.6341319

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-V_T memory in 65nm CMOS. / Meinerzhagen, Pascal; Andersson, Oskar; Mohammadi, Babak et al.
2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. 2012. p. 321-324 6341319 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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