Abstract
Gain-cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded memory implementation, supporting low supply voltages. However, due to its structure, the readout scheme is slow and requires a high precision external reference voltage to improve performance. In this work, we propose a novel bitcell featuring a differential readout mechanism for high frequency operation without the need for an external voltage supply. A 16 kbit memory macro was implemented in 65nm CMOS bulk technology offering up to 3x improvement in access time compared to standard GC-eDRAM solutions and similar read time to SRAM bitcells, while providing up-to 30% reduction in bitcell area compared to standard SRAM solution.
| Original language | English |
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| Title of host publication | 2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798350386301 |
| DOIs | |
| State | Published - 2024 |
| Event | 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024 - Larnaca, Cyprus Duration: 9 Jun 2024 → 12 Jun 2024 |
Publication series
| Name | 2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024 |
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Conference
| Conference | 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024 |
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| Country/Territory | Cyprus |
| City | Larnaca |
| Period | 9/06/24 → 12/06/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- GC-eDRAM
- Low Power
- differential readout
- embedded Memory
- gain cells
- logic-compatible eDRAM