A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

Oskar Andersson; Babak Mohammadi; Pascal Meinerzhagen; Joachim Neves Rodrigues

doi:10.1109/ESSCIRC.2014.6942067

A 35 fJ/bit-access sub-V_T memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Joachim Neves Rodrigues

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

A 128×32 bit ultra-low power (ULP) memory with one read and one write port is presented. A full-custom standard-cell compliant dual-bit latch with two integrated NAND-gates was designed. The NAND-gate realizes the first stage of a read multiplexer. A dense layout reduces the physical cell area by 56 %, compared to a pure commercial standard-cell equivalent. Effectively, an overall memory area reduction of 32%is achieved. The gates are integrated into a digital standard-cell based memory (SCM) flow. Silicon measurements show correct read and write operation deep in the subthreshold domain (sub-V_T), down to 370mV, and data is retained down to 320mV. At the energy minimum voltage (450 mV) the memory dissipates 35 fJ/operation.

Original language	English
Title of host publication	ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
Editors	Pietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso
Publisher	IEEE Computer Society
Pages	243-246
Number of pages	4
ISBN (Electronic)	9781479956944
DOIs	https://doi.org/10.1109/ESSCIRC.2014.6942067
State	Published - 31 Oct 2014
Externally published	Yes
Event	40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy Duration: 22 Sep 2014 → 26 Sep 2014

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	40th European Solid-State Circuit Conference, ESSCIRC 2014
Country/Territory	Italy
City	Venezia Lido
Period	22/09/14 → 26/09/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Funding

Funders	Funder number
Swiss National Science Foundation	PP002-119057

Access to Document

10.1109/ESSCIRC.2014.6942067

Cite this

Andersson, O., Mohammadi, B., Meinerzhagen, P., & Rodrigues, J. N. (2014). A 35 fJ/bit-access sub-V_T memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. In P. Andreani, A. Bevilacqua, & G. Meneghesso (Eds.), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference (pp. 243-246). Article 6942067 (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2014.6942067

Andersson, Oskar ; Mohammadi, Babak ; Meinerzhagen, Pascal et al. / A 35 fJ/bit-access sub-V_T memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. editor / Pietro Andreani ; Andrea Bevilacqua ; Gaudenzio Meneghesso. IEEE Computer Society, 2014. pp. 243-246 (European Solid-State Circuits Conference).

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abstract = "A 128×32 bit ultra-low power (ULP) memory with one read and one write port is presented. A full-custom standard-cell compliant dual-bit latch with two integrated NAND-gates was designed. The NAND-gate realizes the first stage of a read multiplexer. A dense layout reduces the physical cell area by 56 %, compared to a pure commercial standard-cell equivalent. Effectively, an overall memory area reduction of 32%is achieved. The gates are integrated into a digital standard-cell based memory (SCM) flow. Silicon measurements show correct read and write operation deep in the subthreshold domain (sub-VT), down to 370mV, and data is retained down to 320mV. At the energy minimum voltage (450 mV) the memory dissipates 35 fJ/operation.",

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Andersson, O, Mohammadi, B, Meinerzhagen, P & Rodrigues, JN 2014, A 35 fJ/bit-access sub-V_T memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. in P Andreani, A Bevilacqua & G Meneghesso (eds), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference., 6942067, European Solid-State Circuits Conference, IEEE Computer Society, pp. 243-246, 40th European Solid-State Circuit Conference, ESSCIRC 2014, Venezia Lido, Italy, 22/09/14. https://doi.org/10.1109/ESSCIRC.2014.6942067

A 35 fJ/bit-access sub-V_T memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. / Andersson, Oskar; Mohammadi, Babak; Meinerzhagen, Pascal et al.
ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. ed. / Pietro Andreani; Andrea Bevilacqua; Gaudenzio Meneghesso. IEEE Computer Society, 2014. p. 243-246 6942067 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Andersson O, Mohammadi B, Meinerzhagen P, Rodrigues JN. A 35 fJ/bit-access sub-V_T memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. In Andreani P, Bevilacqua A, Meneghesso G, editors, ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. IEEE Computer Society. 2014. p. 243-246. 6942067. (European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.2014.6942067