A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Joachim Neves Rodrigues

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

A 128×32 bit ultra-low power (ULP) memory with one read and one write port is presented. A full-custom standard-cell compliant dual-bit latch with two integrated NAND-gates was designed. The NAND-gate realizes the first stage of a read multiplexer. A dense layout reduces the physical cell area by 56 %, compared to a pure commercial standard-cell equivalent. Effectively, an overall memory area reduction of 32%is achieved. The gates are integrated into a digital standard-cell based memory (SCM) flow. Silicon measurements show correct read and write operation deep in the subthreshold domain (sub-VT), down to 370mV, and data is retained down to 320mV. At the energy minimum voltage (450 mV) the memory dissipates 35 fJ/operation.

Original languageEnglish
Title of host publicationESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
EditorsPietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso
PublisherIEEE Computer Society
Pages243-246
Number of pages4
ISBN (Electronic)9781479956944
DOIs
StatePublished - 31 Oct 2014
Externally publishedYes
Event40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy
Duration: 22 Sep 201426 Sep 2014

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833

Conference

Conference40th European Solid-State Circuit Conference, ESSCIRC 2014
Country/TerritoryItaly
CityVenezia Lido
Period22/09/1426/09/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

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