Abstract
This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamp) with Miller compensation, using a third stage that acts as output buffer to drive large loads. The TSMC 0.18μm PDK was used for the design, simulation and implementation in Cadence Virtuoso. The opamp exhibits 20μW power consumption with a 1-V rail-to-rail supply. Post layout simulation shows a unity gain bandwidth (UGBW) of 69.18 MHz (Av = 49.63dB) with a phase margin (PM) larger than 86° and a Slew rate of 19.87μV/s making our design suitable for small and large signal applications.
Original language | English |
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Title of host publication | ETCM 2021 - 5th Ecuador Technical Chapters Meeting |
Editors | Monica Karel Huerta, Sebastian Quevedo, Carlos Monsalve |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781665441414 |
DOIs | |
State | Published - 12 Oct 2021 |
Externally published | Yes |
Event | 5th IEEE Ecuador Technical Chapters Meeting, ETCM 2021 - Cuenca, Ecuador Duration: 12 Oct 2021 → 15 Oct 2021 |
Publication series
Name | ETCM 2021 - 5th Ecuador Technical Chapters Meeting |
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Conference
Conference | 5th IEEE Ecuador Technical Chapters Meeting, ETCM 2021 |
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Country/Territory | Ecuador |
City | Cuenca |
Period | 12/10/21 → 15/10/21 |
Bibliographical note
Publisher Copyright:© 2021 IEEE.
Keywords
- 0.18 μ m
- cadence virtuoso
- high-performance
- internet of things (IoT)
- low-cost
- miller compensation
- operational amplifier
- post-layout simulation
- stability