A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm

Yizhak Shifman; Yoel Krupnik; Udi Virobnik; Ahmad Khairi; Yosi Sanhedrai; Ariel Cohen

doi:10.1109/A-SSCC47793.2019.9056969

A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm

Yizhak Shifman, Yoel Krupnik, Udi Virobnik, Ahmad Khairi, Yosi Sanhedrai, Ariel Cohen

Intel

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

A differential buffer for high bandwidth (BW), Time-Interleaved Analog to Digital Converters (TI ADCs) is described. The buffer, nested between Track and Hold (TH) circuits, drives the ADC input signal to the individual sub ADCs. A differential, super source-follower based architecture is utilized in the buffer. This architecture features high power supply rejection ratio (PSRR) together with high BW, low power consumption and low Inter-Symbol Interference (ISI). The buffer was fabricated in 10nm Intel process as a part of a 112Gb/s SerDes receiver. A unique method was developed to accurately measure the buffer's output waveform. Measurements show a BW of 9.7GHz, PSRR of 43dB and power consumption of 1.64mW, which is a 68% power reduction compared to the prior art.

Original language	English
Title of host publication	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	235-238
Number of pages	4
ISBN (Electronic)	9781728151069
DOIs	https://doi.org/10.1109/A-SSCC47793.2019.9056969
State	Published - Nov 2019
Externally published	Yes
Event	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China Duration: 4 Nov 2019 → 6 Nov 2019

Publication series

Name	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Volume	2019-November

Conference

Conference	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/Territory	China
City	Macao
Period	4/11/19 → 6/11/19

Bibliographical note

Publisher Copyright:
© IEEE 2019

Keywords

Buffer
Source follower
Time interleaved adc

Access to Document

10.1109/A-SSCC47793.2019.9056969

Cite this

Shifman, Y., Krupnik, Y., Virobnik, U., Khairi, A., Sanhedrai, Y., & Cohen, A. (2019). A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 (pp. 235-238). Article 9056969 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019; Vol. 2019-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC47793.2019.9056969

Shifman, Yizhak ; Krupnik, Yoel ; Virobnik, Udi et al. / A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm. Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 235-238 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019).

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title = "A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm",

abstract = "A differential buffer for high bandwidth (BW), Time-Interleaved Analog to Digital Converters (TI ADCs) is described. The buffer, nested between Track and Hold (TH) circuits, drives the ADC input signal to the individual sub ADCs. A differential, super source-follower based architecture is utilized in the buffer. This architecture features high power supply rejection ratio (PSRR) together with high BW, low power consumption and low Inter-Symbol Interference (ISI). The buffer was fabricated in 10nm Intel process as a part of a 112Gb/s SerDes receiver. A unique method was developed to accurately measure the buffer's output waveform. Measurements show a BW of 9.7GHz, PSRR of 43dB and power consumption of 1.64mW, which is a 68% power reduction compared to the prior art.",

keywords = "Buffer, Source follower, Time interleaved adc",

author = "Yizhak Shifman and Yoel Krupnik and Udi Virobnik and Ahmad Khairi and Yosi Sanhedrai and Ariel Cohen",

note = "Publisher Copyright: {\textcopyright} IEEE 2019; 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 ; Conference date: 04-11-2019 Through 06-11-2019",

year = "2019",

month = nov,

doi = "10.1109/A-SSCC47793.2019.9056969",

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Shifman, Y, Krupnik, Y, Virobnik, U, Khairi, A, Sanhedrai, Y & Cohen, A 2019, A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm. in Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019., 9056969, Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, vol. 2019-November, Institute of Electrical and Electronics Engineers Inc., pp. 235-238, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macao, China, 4/11/19. https://doi.org/10.1109/A-SSCC47793.2019.9056969

A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm. / Shifman, Yizhak; Krupnik, Yoel; Virobnik, Udi et al.
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 235-238 9056969 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019; Vol. 2019-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Virobnik, Udi

AU - Khairi, Ahmad

AU - Sanhedrai, Yosi

AU - Cohen, Ariel

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N2 - A differential buffer for high bandwidth (BW), Time-Interleaved Analog to Digital Converters (TI ADCs) is described. The buffer, nested between Track and Hold (TH) circuits, drives the ADC input signal to the individual sub ADCs. A differential, super source-follower based architecture is utilized in the buffer. This architecture features high power supply rejection ratio (PSRR) together with high BW, low power consumption and low Inter-Symbol Interference (ISI). The buffer was fabricated in 10nm Intel process as a part of a 112Gb/s SerDes receiver. A unique method was developed to accurately measure the buffer's output waveform. Measurements show a BW of 9.7GHz, PSRR of 43dB and power consumption of 1.64mW, which is a 68% power reduction compared to the prior art.

AB - A differential buffer for high bandwidth (BW), Time-Interleaved Analog to Digital Converters (TI ADCs) is described. The buffer, nested between Track and Hold (TH) circuits, drives the ADC input signal to the individual sub ADCs. A differential, super source-follower based architecture is utilized in the buffer. This architecture features high power supply rejection ratio (PSRR) together with high BW, low power consumption and low Inter-Symbol Interference (ISI). The buffer was fabricated in 10nm Intel process as a part of a 112Gb/s SerDes receiver. A unique method was developed to accurately measure the buffer's output waveform. Measurements show a BW of 9.7GHz, PSRR of 43dB and power consumption of 1.64mW, which is a 68% power reduction compared to the prior art.

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Shifman Y, Krupnik Y, Virobnik U, Khairi A, Sanhedrai Y, Cohen A. A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 235-238. 9056969. (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). doi: 10.1109/A-SSCC47793.2019.9056969

A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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