A 1.64mW Differential super source-follower buffer with 9.7ghz bw and 43db psrr for time- interleaved adc applications in 10nm

Yizhak Shifman, Yoel Krupnik, Udi Virobnik, Ahmad Khairi, Yosi Sanhedrai, Ariel Cohen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

A differential buffer for high bandwidth (BW), Time-Interleaved Analog to Digital Converters (TI ADCs) is described. The buffer, nested between Track and Hold (TH) circuits, drives the ADC input signal to the individual sub ADCs. A differential, super source-follower based architecture is utilized in the buffer. This architecture features high power supply rejection ratio (PSRR) together with high BW, low power consumption and low Inter-Symbol Interference (ISI). The buffer was fabricated in 10nm Intel process as a part of a 112Gb/s SerDes receiver. A unique method was developed to accurately measure the buffer's output waveform. Measurements show a BW of 9.7GHz, PSRR of 43dB and power consumption of 1.64mW, which is a 68% power reduction compared to the prior art.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages235-238
Number of pages4
ISBN (Electronic)9781728151069
DOIs
StatePublished - Nov 2019
Externally publishedYes
Event15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China
Duration: 4 Nov 20196 Nov 2019

Publication series

NameProceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Volume2019-November

Conference

Conference15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/TerritoryChina
CityMacao
Period4/11/196/11/19

Bibliographical note

Publisher Copyright:
© IEEE 2019

Keywords

  • Buffer
  • Source follower
  • Time interleaved adc

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