A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Keyphrases

• 90-nm CMOS Technology 100%
• Block Size 33%
• Clock Frequency 33%
• CMOS ASIC 33%
• Decoder 100%
• Energy Efficiency 66%
• IEEE 802.11n 100%
• Iter 100%
• Low Power 33%
• Low-density Parity-check Codes 100%
• Maximum Throughput 33%
• Min-max Algorithm 33%
• Offset Min-Sum 33%
• Operating Voltage 33%
• Precoding Matrix 33%
• Quasi-cyclic 100%
• Register Transfer Level 33%

Engineering

• Application Specific Integrated Circuit 50%
• Blocklength 50%
• Clock Frequency 50%
• Energy Conservation 100%
• Energy Efficiency 100%
• Implementation Level 50%
• Measured Energy 50%
• Operating Voltage 50%

Computer Science

• Application Specific Integrated Circuit 50%
• Clock Frequency 50%
• Energy Efficiency 100%
• min-sum algorithm 50%
• Register-Transfer-Level Implementation 50%