A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

C. Roth, P. Meinerzhagen, C. Studer, A. Burg

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

32 Scopus citations

Abstract

We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11n). The register-transfer-level implementation has been optimized for best energy efficiency. The corresponding 90nm CMOS ASIC has a core area of 1.77mm 2 and achieves a maximum throughput of 680 Mbps at 346 MHz clock frequency and 10 decoding iterations. The measured energy efficiency is 15.8 pJ/bit/iteration at a nominal operating voltage of 1.0V.

Original languageEnglish
Title of host publication2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages313-316
Number of pages4
DOIs
StatePublished - 2010
Externally publishedYes
Event2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China
Duration: 8 Nov 201010 Nov 2010

Publication series

Name2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Conference

Conference2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Country/TerritoryChina
CityBeijing
Period8/11/1010/11/10

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