TY - GEN
T1 - A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS
AU - Roth, C.
AU - Meinerzhagen, P.
AU - Studer, C.
AU - Burg, A.
PY - 2010
Y1 - 2010
N2 - We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11n). The register-transfer-level implementation has been optimized for best energy efficiency. The corresponding 90nm CMOS ASIC has a core area of 1.77mm 2 and achieves a maximum throughput of 680 Mbps at 346 MHz clock frequency and 10 decoding iterations. The measured energy efficiency is 15.8 pJ/bit/iteration at a nominal operating voltage of 1.0V.
AB - We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11n). The register-transfer-level implementation has been optimized for best energy efficiency. The corresponding 90nm CMOS ASIC has a core area of 1.77mm 2 and achieves a maximum throughput of 680 Mbps at 346 MHz clock frequency and 10 decoding iterations. The measured energy efficiency is 15.8 pJ/bit/iteration at a nominal operating voltage of 1.0V.
UR - http://www.scopus.com/inward/record.url?scp=79952831255&partnerID=8YFLogxK
U2 - 10.1109/ASSCC.2010.5716618
DO - 10.1109/ASSCC.2010.5716618
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AN - SCOPUS:79952831255
SN - 9781424482979
T3 - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
SP - 313
EP - 316
BT - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
T2 - 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Y2 - 8 November 2010 through 10 November 2010
ER -