A 14.3pW sub-threshold 2T gain-cell eDRAM for ultra-low power IoT applications in 28nm FD-SOI

Robert Giterman, Adam Teman, Alexander Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Internet of Things (IoT) applications, such as biomedical sensing, often require on-chip embedded memories, which dominate both the silicon area and power of these applications [1, 2]. To adhere to the ultra-low power (ULP) requirements of IoT applications, supply voltage ( VDD)scaling down to the sub-threshold voltage ( VT)region can be used to significantly reduce both the static and dynamic power consumption of these applications. However, embedded memories, typically implemented with 6T SRAM macros, suffer from decreased noise margins and become unreliable at near-VTsupply voltages [2-4].

Original languageEnglish
Title of host publication2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538676264
DOIs
StatePublished - 2 Jul 2018
Event2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States
Duration: 15 Oct 201818 Oct 2018

Publication series

Name2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
Country/TerritoryUnited States
CityBurlingame
Period15/10/1818/10/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Fingerprint

Dive into the research topics of 'A 14.3pW sub-threshold 2T gain-cell eDRAM for ultra-low power IoT applications in 28nm FD-SOI'. Together they form a unique fingerprint.

Cite this