A 13T radiation hardened SRAM bitcell for low-voltage operation

With the increasing demand for ultra-low power memories, and in light of transistor scaling, the Single-Event Upset (SEU) has become a serious problem and therefore an integral aspect of memory cell design [1]. SEUs occur when an energetic particle hits and passes through a semiconductor material, potentially causing a bit-flip in the memory cell [2], [3]. The energetic particle frees electron-hole pairs along its path in the material as it loses energy. When the particle hits a reverse biased pn-junction, such as a transistor diffusion, the injected charge is transported by drift and causes a transient current pulse that can change the node voltage. Data loss occurs when the collected charge exceeds the critical charge (Qcrit) that is stored in the sensitive node. The charge deposited by a particle strike can be calculated from the integral of the transient current pulse, and Qcrit is defined as the minimum charge deposited in a sensitive node that results in memory bit flip. SEUs and other similar Single Event Effects (SEE) are often considered when designing for space applications and similar high radiation environments; however, due to the reduction of Qcrit with technology scaling [4], SEUs can also occur in standard terrestrial environments at non-negligible rates [5]. Architectural solutions, such as error correction (ECC), are often not effective for small arrays in ultra-low power systems operated at low supply voltages, due to their complexity and performance requirements. Technology solutions, such as SOI, can improve the data reliability but do not entirely solve the SEE problems, and often volume manufacturing is not feasible. Therefore, in this work, we propose a radiation hardened low-voltage memory cell for ultra-low power operation. The proposed 13T bitcell is implemented in a standard 0.18μm CMOS process, and is shown to tolerate upsets with charge deposits as high as 500 fC through a dual-driven internal self-correction mechanism