A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI

Robert Giterman; Adam Teman; Alexander Fish

doi:10.1109/s3s.2017.8308757

A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI

Robert Giterman, Adam Teman, Alexander Fish

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

The silicon area of ultra-low power (ULP) applications is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications [1]. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications [2]. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at near-threshold operating voltages [3-6].

Original language	English
Title of host publication	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
ISBN (Electronic)	9781538637654
DOIs	https://doi.org/10.1109/s3s.2017.8308757
State	Published - 2 Jul 2017
Event	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, United States Duration: 16 Oct 2017 → 18 Oct 2017

Publication series

Name	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Volume	2018-March

Conference

Conference	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Country/Territory	United States
City	Burlingame
Period	16/10/17 → 18/10/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

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10.1109/s3s.2017.8308757

Cite this

Giterman, R., Teman, A., & Fish, A. (2017). A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI. In 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 (pp. 1-3). (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/s3s.2017.8308757

@inproceedings{e511d8fdc66c4b8589e7e81c68ca3b49,

title = "A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI",

abstract = "The silicon area of ultra-low power (ULP) applications is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications [1]. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications [2]. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at near-threshold operating voltages [3-6].",

author = "Robert Giterman and Adam Teman and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 ; Conference date: 16-10-2017 Through 18-10-2017",

year = "2017",

month = jul,

day = "2",

doi = "10.1109/s3s.2017.8308757",

language = "אנגלית",

series = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--3",

booktitle = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",

address = "ארצות הברית",

}

Giterman, R, Teman, A & Fish, A 2017, A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI. in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, vol. 2018-March, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Burlingame, United States, 16/10/17. https://doi.org/10.1109/s3s.2017.8308757

A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI. / Giterman, Robert; Teman, Adam ; Fish, Alexander.
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-3 (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI

AU - Giterman, Robert

AU - Teman, Adam

AU - Fish, Alexander

PY - 2017/7/2

Y1 - 2017/7/2

N2 - The silicon area of ultra-low power (ULP) applications is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications [1]. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications [2]. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at near-threshold operating voltages [3-6].

AB - The silicon area of ultra-low power (ULP) applications is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications [1]. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications [2]. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at near-threshold operating voltages [3-6].

UR - http://www.scopus.com/inward/record.url?scp=85047758257&partnerID=8YFLogxK

U2 - 10.1109/s3s.2017.8308757

DO - 10.1109/s3s.2017.8308757

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:85047758257

T3 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

SP - 1

EP - 3

BT - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

Y2 - 16 October 2017 through 18 October 2017

ER -

A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI

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