A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish

Research output: Contribution to journalArticlepeer-review

17 Scopus citations

Abstract

The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16\times 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

Original languageEnglish
Article number9146537
Pages (from-to)314-317
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume3
DOIs
StatePublished - 2020

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Funding

Manuscript received May 15, 2020; revised July 2, 2020; accepted July 15, 2020. Date of publication July 23, 2020; date of current version September 10, 2020. This article was approved by Associate Editor Stefan Rusu. This work was supported by the Israel Innovation Authority in the frame of the Hiper Consortium. (Corresponding author: Ramiro Taco.) Netanel Shavit, Inbal Stanger, and Alexander Fish are with the Emerging Nanoscaled Integrated Circuits and Systems Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel (e-mail: [email protected]; [email protected]; [email protected]).

FundersFunder number
Israel Innovation Authority

    Keywords

    • Adaptive design
    • digital signal processing (DSP)
    • dual-mode logic (DML)

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