A 0.28¿0.8V 320 fW D-latch for sub-VT memories in 65 nm CMOS

Babak Mohammadi, Oskar Andersson, Pascal Meinerzhagen, Yasser Sherazi, Andreas Burg, Joachim Neves Rodrigues

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power.

Original languageEnglish
Title of host publication2014 IEEE Faible Tension Faible Consommation, FTFC 2014
PublisherIEEE Computer Society
ISBN (Print)9781479937738
DOIs
StatePublished - 2014
Externally publishedYes
Event2014 IEEE Faible Tension Faible Consommation, FTFC 2014 - Monaco, Monaco
Duration: 4 May 20146 May 2014

Publication series

Name2014 IEEE Faible Tension Faible Consommation, FTFC 2014

Conference

Conference2014 IEEE Faible Tension Faible Consommation, FTFC 2014
Country/TerritoryMonaco
CityMonaco
Period4/05/146/05/14

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