65NM RADSAFE™ technology for RC64 and advanced SOCS

The trend of scaling of microelectronic provides certain advantages for space components, as well as some challenges. It enables implementing highly integrated and high performance ASICs, reducing power, area and weight. Scaling also improves the immunity to TID and SEL in most cases, but increases soft error rate significantly. Ramon Chips adopted the 65nm technology for implementing RC64 [1,2], a 64 core DSP for space applications, and for making other future products. The 65nm process node is widely used, very mature, and supported by wide range of IP providers. Thus the need for full custom design of cores and IPs is minimized, and radiation hardening is achievable by mitigating the radiation effects on the available IPs, and developing proprietary IPs only for complementing the available IPs. The RadSafe 65TM technology includes hardened standard cells and I/O libraries, methods for mitigation of radiation effects in COTS IP cores (SRAM, PLL, SERDES, DDR2/3 interface) and adding unique cores for monitoring radiation effects and junction temperature. We had developed RADIC6, a technology development vehicle, for verification of all hard cores and verification of the methodologies and design flow required for RC64. RADIC6 includes the test structures for characterizing the IP cores for immunity to all radiation effects. This paper describes the main elements and IP cores of RadSafe 65TM, as well as the contents of RADIC6 test chip.