Abstract
Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access limitations. In this letter, we present a GC-eDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells and also integrates a replica bit line for optimal access timing to improve performance and power consumption. A 64-kB GC-eDRAM macro was fabricated in a 65-nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 μ s retention time.
Original language | English |
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Pages (from-to) | 170-173 |
Number of pages | 4 |
Journal | IEEE Solid-State Circuits Letters |
Volume | 5 |
DOIs | |
State | Published - 2022 |
Bibliographical note
Publisher Copyright:© 2018 IEEE.
Keywords
- SRAM
- eDRAM
- embedded memory
- gain cell
- refresh
- retention time
- system architecture