4T gain-cell providing unlimited availability through hidden refresh with 1W1R functionality

Einat Levy; Aharon Sfez; Roman Golman; Odem Harel; Adam Teman

doi:10.1109/ISCAS51556.2021.9401416

4T gain-cell providing unlimited availability through hidden refresh with 1W1R functionality

Einat Levy
, Aharon Sfez
, Roman Golman
, Odem Harel
, Adam Teman

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Modern SoCs area and power budgets are often dominated by embedded memories on board of the chip. Gain-cell embedded DRAM is a dense, low power memory solution, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. This work presents a novel gain cell design, with robust dual read mechanism, exploiting GC-eDRAM characteristics for double write throughput, supporting low cost hidden refresh mechanism and 100% array availability, providing continuous 1W1R functionality. A 16 kbit memory macro was implemented in 65nm bulk technology offering up-to 20% reduction in bitcell area compared to standard SRAM solution, and up to 3× area reduction compared to 1R1W memory solutions.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728192017
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401416
State	Published - 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2021-May
ISSN (Print)	0271-4310

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Daegu
Period	22/05/21 → 28/05/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE

Funding

ACKNOWLEDGMENTS This work was kindly supported by the Israel Science Foundation under grant number 996/18.

Funders	Funder number
Israel Science Foundation	996/18

Keywords

1W1R
2W2R
Embedded memory
Gain-cell embedded DRAM (GC-eDRAM)
Hidden refresh
Low power
Retention time

Access to Document

10.1109/ISCAS51556.2021.9401416

Cite this

Levy, E., Sfez, A., Golman, R., Harel, O., & Teman, A. (2021). 4T gain-cell providing unlimited availability through hidden refresh with 1W1R functionality. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Article 9401416 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS51556.2021.9401416

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title = "4T gain-cell providing unlimited availability through hidden refresh with 1W1R functionality",

abstract = "Modern SoCs area and power budgets are often dominated by embedded memories on board of the chip. Gain-cell embedded DRAM is a dense, low power memory solution, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. This work presents a novel gain cell design, with robust dual read mechanism, exploiting GC-eDRAM characteristics for double write throughput, supporting low cost hidden refresh mechanism and 100\% array availability, providing continuous 1W1R functionality. A 16 kbit memory macro was implemented in 65nm bulk technology offering up-to 20\% reduction in bitcell area compared to standard SRAM solution, and up to 3× area reduction compared to 1R1W memory solutions.",

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author = "Einat Levy and Aharon Sfez and Roman Golman and Odem Harel and Adam Teman",

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Levy, E, Sfez, A, Golman, R, Harel, O & Teman, A 2021, 4T gain-cell providing unlimited availability through hidden refresh with 1W1R functionality. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401416, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401416

4T gain-cell providing unlimited availability through hidden refresh with 1W1R functionality. / Levy, Einat; Sfez, Aharon; Golman, Roman et al.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401416 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Golman, Roman

AU - Harel, Odem

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PY - 2021

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N2 - Modern SoCs area and power budgets are often dominated by embedded memories on board of the chip. Gain-cell embedded DRAM is a dense, low power memory solution, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. This work presents a novel gain cell design, with robust dual read mechanism, exploiting GC-eDRAM characteristics for double write throughput, supporting low cost hidden refresh mechanism and 100% array availability, providing continuous 1W1R functionality. A 16 kbit memory macro was implemented in 65nm bulk technology offering up-to 20% reduction in bitcell area compared to standard SRAM solution, and up to 3× area reduction compared to 1R1W memory solutions.

AB - Modern SoCs area and power budgets are often dominated by embedded memories on board of the chip. Gain-cell embedded DRAM is a dense, low power memory solution, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. This work presents a novel gain cell design, with robust dual read mechanism, exploiting GC-eDRAM characteristics for double write throughput, supporting low cost hidden refresh mechanism and 100% array availability, providing continuous 1W1R functionality. A 16 kbit memory macro was implemented in 65nm bulk technology offering up-to 20% reduction in bitcell area compared to standard SRAM solution, and up to 3× area reduction compared to 1R1W memory solutions.

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Levy E, Sfez A, Golman R, Harel O, Teman A. 4T gain-cell providing unlimited availability through hidden refresh with 1W1R functionality. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9401416. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS51556.2021.9401416

4T gain-cell providing unlimited availability through hidden refresh with 1W1R functionality

Abstract

Publication series

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Bibliographical note

Funding

Keywords

Access to Document

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