Abstract
Modern SoCs area and power budgets are often dominated by embedded memories on board of the chip. Gain-cell embedded DRAM is a dense, low power memory solution, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. This work presents a novel gain cell design, with robust dual read mechanism, exploiting GC-eDRAM characteristics for double write throughput, supporting low cost hidden refresh mechanism and 100% array availability, providing continuous 1W1R functionality. A 16 kbit memory macro was implemented in 65nm bulk technology offering up-to 20% reduction in bitcell area compared to standard SRAM solution, and up to 3× area reduction compared to 1R1W memory solutions.
Original language | English |
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Title of host publication | 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781728192017 |
DOIs | |
State | Published - 2021 |
Event | 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021 |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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Volume | 2021-May |
ISSN (Print) | 0271-4310 |
Conference
Conference | 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 |
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Country/Territory | Korea, Republic of |
City | Daegu |
Period | 22/05/21 → 28/05/21 |
Bibliographical note
Funding Information:ACKNOWLEDGMENTS This work was kindly supported by the Israel Science Foundation under grant number 996/18.
Publisher Copyright:
© 2021 IEEE
Keywords
- 1W1R
- 2W2R
- Embedded memory
- Gain-cell embedded DRAM (GC-eDRAM)
- Hidden refresh
- Low power
- Retention time