3D cache hierarchy optimization

Leonid Yavits; Amir Morad; Ran Ginosar

doi:10.1109/3DIC.2013.6702346

3D cache hierarchy optimization

Leonid Yavits, Amir Morad, Ran Ginosar

Technion-Israel Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

3D integration has the potential to improve the scalability and performance of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing 3D CMP cache hierarchy is developed. It allows optimal partitioning of the cache hierarchy levels into 3D silicon layers and optimal allocation of area among cache hierarchy levels under constrained area and power budgets. The optimization framework is extended by incorporating the impact of multithreaded data sharing on the private cache miss rate. An analytical model for cache access time as a function of cache size and a number of 3D partitions is proposed and verified using CACTI simulation.

Original language	English
Title of host publication	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
DOIs	https://doi.org/10.1109/3DIC.2013.6702346
State	Published - 2013
Externally published	Yes
Event	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 - San Francisco, CA, United States Duration: 2 Oct 2013 → 4 Oct 2013

Publication series

Name	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013

Conference

Conference	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
Country/Territory	United States
City	San Francisco, CA
Period	2/10/13 → 4/10/13

Keywords

3D integration
Analytical Performance Models
Cache Hierarchy
Chip Multiprocessor
Resource Allocation Optimization

Access to Document

10.1109/3DIC.2013.6702346

Cite this

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title = "3D cache hierarchy optimization",

abstract = "3D integration has the potential to improve the scalability and performance of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing 3D CMP cache hierarchy is developed. It allows optimal partitioning of the cache hierarchy levels into 3D silicon layers and optimal allocation of area among cache hierarchy levels under constrained area and power budgets. The optimization framework is extended by incorporating the impact of multithreaded data sharing on the private cache miss rate. An analytical model for cache access time as a function of cache size and a number of 3D partitions is proposed and verified using CACTI simulation.",

keywords = "3D integration, Analytical Performance Models, Cache Hierarchy, Chip Multiprocessor, Resource Allocation Optimization",

author = "Leonid Yavits and Amir Morad and Ran Ginosar",

year = "2013",

doi = "10.1109/3DIC.2013.6702346",

language = "אנגלית",

isbn = "9781467364843",

series = "2013 IEEE International 3D Systems Integration Conference, 3DIC 2013",

booktitle = "2013 IEEE International 3D Systems Integration Conference, 3DIC 2013",

note = "2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 ; Conference date: 02-10-2013 Through 04-10-2013",

}

Yavits, L, Morad, A & Ginosar, R 2013, 3D cache hierarchy optimization. in 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013., 6702346, 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013, 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013, San Francisco, CA, United States, 2/10/13. https://doi.org/10.1109/3DIC.2013.6702346

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AB - 3D integration has the potential to improve the scalability and performance of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing 3D CMP cache hierarchy is developed. It allows optimal partitioning of the cache hierarchy levels into 3D silicon layers and optimal allocation of area among cache hierarchy levels under constrained area and power budgets. The optimization framework is extended by incorporating the impact of multithreaded data sharing on the private cache miss rate. An analytical model for cache access time as a function of cache size and a number of 3D partitions is proposed and verified using CACTI simulation.

KW - 3D integration

KW - Analytical Performance Models

KW - Cache Hierarchy

KW - Chip Multiprocessor

KW - Resource Allocation Optimization

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ER -

3D cache hierarchy optimization

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