112-Gb/s PAM4 ADC-Based SERDES Receiver with Resonant AFE for Long-Reach Channels

Yoel Krupnik; Yevgeny Perelman; Itamar Levin; Yosi Sanhedrai; Roee Eitan; Ahmad Khairi; Yizhak Shifman; Yoni Landau; Udi Virobnik; Noam Dolev; Alon Meisler; Ariel Cohen

doi:10.1109/jssc.2019.2959511

112-Gb/s PAM4 ADC-Based SERDES Receiver with Resonant AFE for Long-Reach Channels

Yoel Krupnik, Yevgeny Perelman, Itamar Levin, Yosi Sanhedrai, Roee Eitan, Ahmad Khairi, Yizhak Shifman, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen

Intel

Research output: Contribution to journal › Article › peer-review

59 Scopus citations

Abstract

A 112-Gb/s PAM4 analog-To-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel's 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-Tap feed-forward equalizer (FFE), and a 1-Tap decision-feedback equalizer (DFE), as well as a clock and data recovery (CDR) loop utilizing a 7-GHz digitally controlled oscillator (DCO). Long-reach,-35 dB Nyquist channels are supported by a pre-forward error correction (FEC) bit error rate (BER) of 1e-6, thus making it compatible with existing and projected IEEE Ethernet specifications.

Original language	English
Article number	8952650
Pages (from-to)	1077-1085
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	55
Issue number	4
DOIs	https://doi.org/10.1109/jssc.2019.2959511
State	Published - Apr 2020
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

Funding

Manuscript received August 15, 2019; revised October 28, 2019 and December 4, 2019; accepted December 5, 2019. Date of publication January 8, 2020; date of current version March 26, 2020. This article was approved by Guest Editor Brian Ginsburg. This work was supported by Intel Corporation. (Corresponding author: Ariel Cohen.) Y. Krupnik, I. Levin, Y. Sanhedrai, A. Khairi, Y. Shifman, U. Virobnik, and A. Cohen are with the Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel (e-mail: [email protected]).

Funders	Funder number
Intel Corporation

Keywords

112 Gb/s
PAM4
SAR
analog-To-digital converter (ADC)
feed-forward equalizer (FFE)
serializer/de-serializer transceiver (SERDES)

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10.1109/jssc.2019.2959511

Cite this

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abstract = "A 112-Gb/s PAM4 analog-To-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel's 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-Tap feed-forward equalizer (FFE), and a 1-Tap decision-feedback equalizer (DFE), as well as a clock and data recovery (CDR) loop utilizing a 7-GHz digitally controlled oscillator (DCO). Long-reach,-35 dB Nyquist channels are supported by a pre-forward error correction (FEC) bit error rate (BER) of 1e-6, thus making it compatible with existing and projected IEEE Ethernet specifications.",

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112-Gb/s PAM4 ADC-Based SERDES Receiver with Resonant AFE for Long-Reach Channels

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