TY - JOUR
T1 - 0.45 v and 18 μa/MHZ MCU SOC with advanced adaptive dynamic voltage control (ADVC)
AU - Zangi, Uzi
AU - Feldman, Neil
AU - Hadas, Tzach
AU - Dayag, Noga
AU - Shor, Joseph
AU - Fish, Alexander
N1 - Publisher Copyright:
© 2018 by the authors.
PY - 2018/6
Y1 - 2018/6
N2 - An ultra-low-power MicroController Unit System-on-Chip (MCU SOC) is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC, designed and fabricated in a 40 nm ULP standard CMOS technology, includes the complete Synopsys ARC EM5D core MCU, featuring a full set of DSP instructions and minimizing energy consumption at a wide range of frequencies: 312 K–80 MHz. A number of unique low voltage digital libraries, comprising of approximately 300 logic cells and sequential elements, were used for the MCU SOC design. On-die silicon sensors were utilized to continuously change the operating voltage to optimize power/performance for a given frequency and environmental conditions, and also to resolve yield and life time problems, while operating at low voltages. A First Fail (FFail) mechanism, which can be digitally and linearly controlled with up to 8 bits, detects the failing SOC voltage at a given frequency. The core operates between 0.45–1.1 V volts with a direct battery connection for an input voltage of 1.6–3.6 V. Measurement results show that the peak energy efficiency is 18μW/MHz. A comparison to state-of-the-art commercial SOCs is presented, showing a 3–5× improved current/DMIPS (Dhrystone Million Instructions per second) compared to the next best chip.
AB - An ultra-low-power MicroController Unit System-on-Chip (MCU SOC) is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC, designed and fabricated in a 40 nm ULP standard CMOS technology, includes the complete Synopsys ARC EM5D core MCU, featuring a full set of DSP instructions and minimizing energy consumption at a wide range of frequencies: 312 K–80 MHz. A number of unique low voltage digital libraries, comprising of approximately 300 logic cells and sequential elements, were used for the MCU SOC design. On-die silicon sensors were utilized to continuously change the operating voltage to optimize power/performance for a given frequency and environmental conditions, and also to resolve yield and life time problems, while operating at low voltages. A First Fail (FFail) mechanism, which can be digitally and linearly controlled with up to 8 bits, detects the failing SOC voltage at a given frequency. The core operates between 0.45–1.1 V volts with a direct battery connection for an input voltage of 1.6–3.6 V. Measurement results show that the peak energy efficiency is 18μW/MHz. A comparison to state-of-the-art commercial SOCs is presented, showing a 3–5× improved current/DMIPS (Dhrystone Million Instructions per second) compared to the next best chip.
KW - Adaptive dynamic voltage control (ADVC)
KW - First fails circuit
KW - Low voltage MCU SOC
KW - Subthreshold logic
UR - http://www.scopus.com/inward/record.url?scp=85048297074&partnerID=8YFLogxK
U2 - 10.3390/jlpea8020014
DO - 10.3390/jlpea8020014
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AN - SCOPUS:85048297074
SN - 2079-9268
VL - 8
JO - Journal of Low Power Electronics and Applications
JF - Journal of Low Power Electronics and Applications
IS - 2
M1 - 14
ER -