Research output

Research output per year 1996 2011 2017 2018 2019 2020 2024

• 69 Conference contribution
• 48 Article
• 10 Patent
• 5 Chapter
• 2 More
  • 1 Paper
  • 1 Conference article

Research output per year

Research output per year

Search results

• 2019

  Data-dependent delay circuits

  Fish, A. (Inventor), Levi, I. (Inventor) & Keren, O. (Inventor), 2019, IPC No. US010521530B2, United States Patent and Trademark Office, Patent No. US 10,521,530, Priority No. US15636902

  Research output: Patent

  • Circuit Design 100%
  • Data Delay 100%
  • Delay Circuits 100%
  • Logic Path 75%
  • Logic Circuit 50%

• Information redistribution to reduce side channel leakage

  Keren, O. (Inventor), Fish, A. (Inventor) & Weizman, Y. (Inventor), 2019, Washington, DC: U.S. Patent and Trademark Office, Priority No. PCT application No.: PCT/IL2019/050230

  Research output: Patent

• Randomized logic against side channel attacks

  Keren, O. (Inventor), Avital, M. (Inventor), Levi, I. (Inventor) & Fish, A. (Inventor), 2019, Washington, DC: U.S. Patent and Trademark Office, Priority No. Publication No. US 2019-0028263

  Research output: Patent

• Randomized logic against side channel attacks

  Fish, A. (Inventor), Avital, M. (Inventor), Levy, I. (Inventor) & Osnat, K. (Inventor), 2019, United States Patent and Trademark Office, Priority No. 15/757,658

  Research output: Patent

  • Side-channel Attacks 100%
  • Side Channel Attack 100%
  • Randomization 100%
  • Logic Input 60%
  • Logic Circuit 50%
• 2018

  Compact Bit Generator

  Keren, O. (Inventor), Avital, M. (Inventor), Mordakhay, A. (Inventor), Weizman, Y. (Inventor) & Fish, A. (Inventor), 2018, Washington, DC: U.S. Patent and Trademark Office, Priority No. Application No.: US 16/224,869

  Research output: Patent

• Secured memory

  Keren, O. (Inventor), Levi, I. (Inventor), Giterman, R. (Inventor) & Fish, A. (Inventor), 2018, Washington, DC: Patent and Trademark Office, Priority No. PCT application No: PCT/IL2018/051338

  Research output: Patent
• 2017

  Pseudo-Async design

  Keren, O. (Inventor), Levi, I. (Inventor) & Fish, A. (Inventor), 2017, Washington, DC: U.S. Patent and Trademark Office, Priority No. PCT application No: PCT/IL2017/050732

  Research output: Patent

• Pseudo-Asynchronous digital circuit design

  Fish, A. (Inventor), Levi, I. (Inventor) & Keren, O. (Inventor), 2017, United States Patent and Trademark Office, Priority No. US 16/312,317

  Research output: Patent
• 2016

  Separable robust coding

  Keren, O. (Inventor), Rabii, H. (Inventor), Neumeier, Y. (Inventor), Bodner, Y. (Inventor) & Sdika, T. (Inventor), 2016, Washington, DC: US Patent and Trademark Office, Priority No. Provisional application 62/397,392

  Research output: Patent
• 1999

  Scalar product and parity check

  Osnat, K. (Inventor) & Ofek, E. (Inventor), 1999, DSP Group, Priority No. 6760880

  Research output: Patent