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  • 2001

    Verifying hardware in its software context and vice-versa

    Kurshan, R. P. (Inventor), Levin, V. (Inventor), Minea, M. (Inventor), Peled, D. (Inventor) & Yenigun, H. (Inventor), 2001, USPTO, Patent No. US6209120 B1, Priority No. US 09/172,484

    Research output: Patent

  • 1998

    Message sequence chart analyzer

    Holzmann, G. J. (Inventor) & Peled, D. (Inventor), 1998, USPTO, Patent No. US5812145 A, Priority No. US 08/559,325

    Research output: Patent

  • Static partial order reduction

    Kurshan, R. P. (Inventor), Levin, V. (Inventor), Minea, M. (Inventor), Peled, D. (Inventor) & Yenigun, H. (Inventor), 1998, USPTO, Patent No. US6295515 B1, Priority No. US 09/172,460

    Research output: Patent

  • 1997

    On-the-fly model checking with partial-order state space reduction

    Holzmann, G. J. (Inventor) & Peled, D. (Inventor), 1997, USPTO, Patent No. US5615137 A, Priority No. US 08/667,350

    Research output: Patent

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