Keyphrases
Gain Cell
100%
EDRAM
94%
Spin-transfer Torque Magnetic RAM (STT-MRAM)
35%
Static Random Access Memory
33%
Data Retention Time
31%
Gain-cell Embedded DRAM (GC-eDRAM)
28%
Embedded Memory
27%
Energy Efficient
26%
Transistor
25%
Clockless
24%
Cryogenic Temperature
23%
Bitcell
21%
Double-barrier Magnetic Tunnel Junction
20%
Content-addressable Memory
20%
Read Operation
19%
Low Voltage
17%
Memory Technologies
17%
Write Operation
16%
Modelling Space
16%
Design Space
16%
First-in-first-out
16%
Controller
16%
Bitline
16%
UTBB FD-SOI
14%
Fin Field-effect Transistor (FinFET)
14%
Modeling Tools
14%
Dot Product
13%
Storage Node
13%
Retention Time
12%
Wordline
12%
High-throughput
12%
Order of Magnitude
12%
Memory Architecture
11%
Junction-based
11%
Room Temperature
10%
Logic Compatible
10%
Low Power
9%
Memory Design
9%
Non-volatility
9%
FDSOI Technology
9%
Transistor Model
9%
Power Consumption
9%
Modern Systems
9%
Memory Cell
9%
Approximate Matching
9%
In-memory
9%
CMOS Technology
8%
Area Reduction
8%
65nm CMOS
8%
Standard Cell Library
8%
Engineering
Random Access Memory
55%
Retention Time
51%
Data Retention
43%
Energy Engineering
36%
Spin Transfer
28%
Supply Voltage
21%
Cryogenic Temperature
20%
Magnetic Tunnel Junction
20%
Bit Line
20%
Nodes
18%
Electric Power Utilization
18%
Design Space
16%
Dynamic Random Access Memory
16%
Area Reduction
16%
Room Temperature
15%
Dot Product
12%
Process Variation
11%
Power Budget
10%
Trigger Signal
8%
Interconnects
8%
Error Detection
8%
Electrical Engineering
8%
Single Event Upset
8%
Fits and Tolerances
8%
Design Engineering
8%
Computer Engineering
8%
Design Cycle
8%
Field-Effect Transistor
8%
Silicon on Insulator Technology
8%
Read Voltage
8%
Noise Margin
8%
Cell Design
8%
Limitations
8%
Cycle Frequency
6%
Access Delay
6%
Architectural Transformation
6%
Context Modeling
6%
Process Step
6%
Random Process
6%
Access Time
6%
Optimal Design
6%
Tasks
6%
Design Optimization
6%
Data Signal
6%
Input Port
5%
Output Port
5%
Computer Science
Data Retention
36%
embedded memory
33%
Energy Efficient
27%
Static Random Access Memory
27%
Random Access Memory
27%
Pipelining
24%
Supply Voltage
21%
Content-Addressable Memory
20%
Memory Architecture
18%
High Throughput
16%
Dynamic Random Access Memory
16%
Temporary Memory
16%
Read Operation
12%
Process Variation
12%
Nonvolatile
10%
Integrated Circuits
10%
Cycle Frequency
10%
Circuit Technology
10%
Interdependent Variable
10%
Design Practice
10%
Design Optimization
10%
Complex Task
10%
Write Operation
10%
Memory Technology
9%
Access Pattern
9%
Approximate Matching
9%
Hamming Distance
8%
Dot Product Algorithm
8%
Timing Analysis
8%
First-in-First-Out
8%
Room Temperature
8%
Compression Algorithm
8%
Physical Implementation
8%
Soft Error
8%
Performance Optimization
8%
Routing Congestion
8%
Logic Gate
8%
Performance Improvement
8%
Deep Learning
8%
Performance Loss
8%
Open Source
8%
Power Consumption
5%
Noise Margin
5%
